1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an increase in withstand capacity for static breakdown due to ESD (electrostatic discharge).
2. Description of the Related Art
A device that uses a guard ring having a multiple structure has hitherto been proposed as a high withstand voltage device (see; for instance, Patent Document 1). In Patent Document 1, a semiconductor film made of silicon containing n-type impurities is formed, by means of epitaxial growth, on a semiconductor substrate made of silicon containing n-type impurities. An n-type intermediate concentration layer, an n-type low concentration layer, a p−-type active region, guard rings formed in a multi-structure, a p+-type active region, and an n+-type channel stopper region are formed in the semiconductor film.
By means of the structure, when the device is activated, the outermost guard ring serves as a point for originating the maximum electric charge. However, multiple numbers of guard rings are present and electrically stable while protected by a silicon oxide film. Hence, comparatively heavy load is imposed on intermediate guard rings, thereby reducing field intensity. Thus, a withstand voltage structure is realized.
A mesa semiconductor device, such as that shown in FIG. 11, has been known as another high withstand voltage device. In the semiconductor substrate of the mesa semiconductor device, a plurality of semiconductor crystal thin films forming an epitaxial layer are formed over an upper surface of a base layer 1; an n-type semiconductor region 2 made of an n-type semiconductor layer is formed over an upper surface of the base layer 1 made of an n-type semiconductor layer; a p-type semiconductor region 3 made of a p-type semiconductor layer is formed over an upper surface of the n-type semiconductor region 2; and the n-type semiconductor region 2 and the p-type semiconductor region 3 form a p-n junction. An anode electrode 4 is formed over an upper surface of the p-type semiconductor region 3 making up one principal surface of the semiconductor substrate, and a cathode electrode 5 is formed over a lower surface of the base layer 1 forming the other principal surface of the semiconductor substrate. A mesa area 6 making up a concave slope is formed along a circumference of the semiconductor substrate. An oxide film 8, such as SiO2, is provided so as to cover the mesa area 6, and a protective film 7 is provided so as to cover the oxide film 8.    Patent Document 1: JP-A-2005-183605    Patent Document 2: JP-A-2008-130622
Incidentally, in the diode of Patent Document 1, an electric field concentrates on the guard rings when a reverse bias voltage is applied to the diode. An electric field particularly concentrates on corners in the guard rings. Therefore, when a surge current flows through a device, the highest concentration of an electric field arises in the corners of the guard rings, which may cause local breakdown. Thus, the diode does not have sufficient withstand capacity for static breakdown due to an ESD.
When a reverse bias voltage is applied to the mesa semiconductor device in FIG. 10; i.e., a mesa diode, the p-type semiconductor region 3 made of a p-type semiconductor layer is present over the entire surface of the active region on one principal surface of the semiconductor substrate. Hence, a location where the highest concentration of electric field arises is an area in a mesa area where an end of the p-n junction interface is exposed.